JSSC 2019第12期Data Converters65nmSAR ADCTDC

A 06-V 13-bit 20-MSs Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-E

一种0.6V供电、13位20MS/s的TDC辅助SAR ADC，具有PVT鲁棒性和速度增强技术。

65nm CMOS, 0.6V, 20MS/s, 71.0dB SNDR, 89.5dB SFDR

低功耗SAR ADCTDC辅助PVT鲁棒性速度增强

▸VTC和TDC实现内在PVT鲁棒性

▸电压域和时间域速度增强技术

▸检测-跳过切换和偏移位偏移方案提升线性度

Abstract

This article presents a low power-supplied 13-bit 20- MS/s time-to-digital converter (TDC)-assisted successive approx- imation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed- enhanced techniques accelerate the ﬁrst- and second-stage ADC conv