A 30-GHz Digital Sub-Sampling Fractional- N PLL With 2386-dB Jitter-Power Figur

Abstract

This article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter- wave and RF synthesizers, using a low-cost 65-nm LP CMOS technology. The circuit is a digitally intensive fractional- N phase-locked loop, which combines a sub-sampling bang-bang phase detector, a low-power divider-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digita