← 返回 JSSC 论文列表JSSC 2019第12期Data Converters40nmSAR ADC
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC
提出一种无需校准的时间交织四阶噪声整形SAR ADC，扩展带宽并保持高能效。
40nm CMOS, 50MHz带宽, 70.4dB SNDR, 13mW功耗, 0.06mm²面积
噪声整形SAR时间交织高阶噪声传递无校准高能效ADC
▸多通道中间反馈实现高阶噪声传递函数
▸利用冗余和NTF系数优化避免量化过载
▸采用求和预放大器和共享反馈总线简化误差反馈
Abstract
Noise-shaping SAR (NS-SAR) is an emerging analog
to digital converter (ADC) architecture that offers both high-
resolution and high-energy efficiency. Despite these advantages,
oversampling limits the useful bandwidth of NS-SAR ADCs. This
article introduces a robust and practical interleaving architecture
that overcomes this bandwidth limitation. Midway feedback
to multiple successive-approximation conversion phases enables
a realizable time-interleaved noise-shaped (TINS) system. The
inherent de