A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary

Abstract

This article proposes a complementary distributed power amplifier (DPA) using stacked gain cells with multiple input driving signals. The stack multi-drive compensates for the increasing input transmission line (TL) and stack losses as frequency increases and results in bandwidth (BW) extension with a flat gain response. The technique simultaneously increases the gain-BW (GBW) product and the output power at high frequencies while maintaining a smaller chip area compared with the conventional DPA design. A broadband active splitter is introduced before the output stage to create two complementary distributed paths which are exploited for AM–AM and AM–PM non-linearity compensation. The CMOS DPA is implemented in 45-nm RFSOI with a core area of 0.31 mm 2. The amplifier has a 23-dB gain and 108-GHz 3-dB BW from true-dc frequency with no need for external bias tees. The DPA maintains a P 1d B and PSAT over 16.9 and 18.4 dBm, respectively, from dc-to-70 GHz, with a 70-GHz P SAT 3-dB BW. When operated with modulated signals, the DPA provides over 100 Gb/s in both 64-QAM and PAM-4 modulations. To the best of our knowledge, the CMOS DPA reports the highest GBW (1.525 THz), the highest data rate in 64-QAM for carriers up to 59 GHz, and the highest single- ended output swing in PAM-4 modulation.