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An Ultra-Low-Jitter mmW-Band Frequency Synthesizer Based on Digital Subsampling
采用数字子采样技术的毫米波频段超低抖动频率合成器设计
28-31GHz, <80fs rms抖动, <-40dBc IPN, 41.8mW功耗
毫米波频率合成器数字子采样超低抖动CMOS
▸级联架构实现毫米波频段超低抖动输出
▸采用最优间距电压比较器抑制量化噪声
▸GHz波段数字子采样锁相环决定整体性能
Abstract
This article presents a cascaded architecture of a
frequency synthesizer to generate ultra-low-jitter output signals
in a millimeter-wave (mmW) frequency band from 28 to 31 GHz.
The mmW-band injection-locked frequency multiplier (ILFM)
placed at the second stage has a wide bandwidth so that
the performance of the jitter of this frequency synthesizer is
determined by the GHz-band, digital subsampling phase-locked
loop (SSPLL) at the first stage. To suppress the quantization
noise of the digital SS