JSSC 2019第12期RF & Wireless65nm

Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Pr

65nm CMOS工艺下实现亚纳瓦级唤醒接收器，采用栅极偏置自混频器和时间编码信号处理技术

434MHz时-79.1dBm灵敏度/420pW功耗，1.016GHz时-74dBm灵敏度/470pW功耗

唤醒接收器自混频器时间编码亚纳瓦功耗CMOS

▸创新点1：栅极偏置自混频器技术通过40级MOS自混频器结构结合栅极偏置优化，显著提升接收机灵敏度至-79.1dBm（434MHz）和-74dBm（1.016GHz），属于电路级创新

▸创新点2：时间编码模拟信号技术实现了高效匹配滤波器设计，通过数字域时间编码替代传统模拟处理，在保持-79.1dBm灵敏度的同时将功耗控制在420pW，属于系统架构创新

▸创新点3：直流偏移消除环路采用创新的反馈机制，有效抑制基带电路直流漂移，使整体功耗降至亚纳瓦级（470pW@1.016GHz），属于电路级功耗优化创新

▸创新点4：0.4V超低电压工作模式通过全集成65nm LP CMOS工艺实现，在维持110ms延迟的同时突破传统唤醒接收机的功耗极限（<500pW），属于工艺与系统协同创新

Abstract

A fully integrated wake-up receiver in 65-nm low- power (LP) CMOS technology is presented. The receiver’s RF front end consists of a 40-stage MOS self-mixer using gate biasing to optimize the sensitivity; the baseband circuits use time-encoded analog signals to efﬁciently implement a matched ﬁlter with a DC offset cancellation loop at minimal power consumption. When operating at 434 MHz, the receiver has a −79.1-dBm sensitivity with a 110-ms latency while consuming 420 pW from 0.4 V . When opera