A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Abstract

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorpo- rates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal proces- sor (DSP) following a 10-bit time-interleaved pipelined successive- approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.