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A 28-nm Compute SRAM With Bit-Serial Logic-Arithmetic Operations for Programmabl
提出一种28纳米混合内存计算SRAM，支持多种位宽和运算类型，适用于物联网处理器。
28nm CMOS, 1.1V, 475MHz, 30 GOPS, 1.4 GFLOPS, 0.56 TOPS/W (8-bit乘法), 5.27 TOPS/W (8-bit加法)
内存计算SRAM物联网处理器位串行运算能效优化
▸8T可转置位单元设计
▸支持向量化位串行内存内算术运算
▸灵活支持从单比特到32/64比特的多种位宽
Abstract
This article proposes a general-purpose hybrid
in-/near-memory compute SRAM (CRAM) that combines an
8T transposable bit cell with vector-based, bit-serial in-memory
arithmetic to accommodate a wide range of bit-widths, from
single to 32 or 64 bits, as well as a complete set of operation types,
including integer and floating-point addition, multiplication, and
division. This approach provides the flexibility and programma-
bility necessary for evolving software algorithms ranging from
neural networ