A 28-nm Compute SRAM With Bit-Serial Logic/ Arithmetic Operations for Programmable In-Memory Vector Computing Jingcheng Wang , Student Member , IEEE,X i a o w e iW a n g, Student Member , IEEE, Charles Eckert , Student Member , IEEE, Arun Subramaniyan , Student Member , IEEE

Abstract

This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programma- bility necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multipli- cation and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz.