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A 2 --times- 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Pr
开发了首个基于内存计算方法的2×30k自旋多芯片CMOS退火处理器，用于解决大规模组合优化问题。
40nm CMOS, 22μs退火时间, 比传统CPU快2.6×10^4倍
CMOS退火处理器多芯片内存计算组合优化自旋电路
▸可扩展高精度自旋算子用于本地通信
▸使用直接访问SRAM的高度集成自旋电路
▸不影响退火过程运行时或结果的低延迟芯片间接口
Abstract
The world’s first 2 × 30k-spin multi-chip CMOS
annealing processor (AP)—based on the processing-in-memory
approach for solving large-scale combinatorial optimization
problem—was developed. To expand the bit width of coefficients
and enhance the scalability of the AP, it has three key features:
an expandable and high-accuracy spin operator for local com-
munication, a highly integrated spin circuit using direct access
to SRAM, and a low-latency inter-chip interface that does not
affect the runtime