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JSSC 2020第1期Other65nm

A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating

提出一种65nm混合数字模拟信号计算平台,支持群机器人算法,能效随数据路径分辨率可调。
65nm CMOS, 峰值能效9.1 TOPS/W(3b)至1.1 TOPS/W(8b)
低功耗边缘智能群机器人混合数字模拟信号能效可调65nm CMOS
支持群机器人算法的混合数字模拟信号计算平台
能效随数据路径分辨率及群规模可调
同时支持基于物理模型和学习的算法
Abstract
Low-power edge-intelligence is leading to spectac- ular advances in smart sensors, actuators, and human–machine interfaces. In particular, energy efficiency is driving key advances in robotics, where low-power computation is augmented with smart control and mechanical systems to enable small-sized and intelligent drones, unmanned aerial vehicles (UA Vs), micro-sized cars, and so on with applications in surveillance, disaster relief, and reconnaissance. Furthermore, for a variety of tasks, swarms of robots are often used as opposed to the individual robots. This article presents an energy-efficient computing platform that can enable a sample class of algorithms for swarm robotics. We demonstrate that both physical-model-based algorithms as well as learning-based algorithms can be supported on the same computing platform. We also demonstrate that with changing swarm sizes, the number of bits required to compute also scales. We take advantage of this observation to propose a hybrid-digital- mixed-signal computing platform, whose energy efficiency scales with the resolution of the data path and hence the swarm size. Measurements on a 65-nm CMOS test-chip demonstrate a peak energy efficiency of 9.1 TOPS/W at a 3-b resolution, and it scales down to 1.1 TOPS/W at an 8-b resolution.