JSSC 2020第1期Clocking & PLLs1xnmDRAM

A 75 Gb-s-pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

本文介绍了一种采用1xnm DRAM工艺的8Gb LPDDR5 SDRAM，通过多种高速和低功耗技术实现7.5 Gb/s/pin的带宽。

7.5 Gb/s/pin, 8-Gb, 21% read power reduction, 33% write power reduction, 25% self-refresh power reduction

LPDDR5SDRAM低功耗高速ZQ校准

▸创新点1：采用抗电源噪声的WCK时钟方案（方法创新），通过优化时钟分配网络和电源滤波设计，在7.5 Gb/s/pin高速传输下实现低于LPDDR4X的时钟抖动（<0.15 UI），提升信号完整性

▸创新点2：提出非目标ODT模式（系统创新），在双Rank系统中动态调整终端电阻值，抑制反射噪声达40%，使眼图高度改善35%，支持更高频率的稳定数据传输

▸创新点3：深度睡眠模式（DSM）设计（电路创新），通过关闭非必要电压发生器将自刷新功耗降低25%，漏电流减少至常规模式的1/8，同时保持关键存储数据不丢失

▸创新点4：动态电压频率缩放（DVFS）与零数据写入优化（联合创新），读写操作功耗分别降低21%和33%，在4.266 Gb/s速率下通过电压/频率自适应调节节省15%动态功耗

Abstract

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is imple- mented in a 1xnm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power noise is adopted and a non-target ODT mode is proposed to reduce reﬂection noise in a two-rank system. A couple of techniques are proposed for saving power. To reduce self-refresh power, this chip supports deep sleep mode (DSM). In DSM, the leakage current of