A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors Xin Si , Student Member , IEEE, Jia-Jing Chen, Y ung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Y en-Cheng Chiu, Wei-Chen Wei, Ssu-Y en Wu, Xiaoyu Sun , Student Member , IEEE, Rui Liu , Student Member , IEEE, Shimeng Y u , Senior Member , IEEE, Ren-Shuo Liu, Chih-Cheng Hsieh

Abstract

Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and- accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 × 60 b T8T unit- macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output.