Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Y u Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Y uan Huang, Ting-Wei Chang, Tung-Cheng Chang, Hui-Y ao Kao, Y en-Cheng Chiu, Chun-Ying Lee, Y a-Chin King , Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh

Abstract

Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelli- gence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area- latency-energy tradeoff for multibit MAC operations, pattern- dependent degradation in signal margin, and small read margin. To overcome these challenges, this article proposes the follow- ing: 1) a serial-input non-weighted product (SINWP) structure; 2) a down-scaling weighted current translator (DSWCT) and positive–negative current-subtractor (PN-ISUB); 3) a current- aware bitline clamper (CABLC) scheme; and 4) a triple-margin small-offset current-mode sense amplifier (TMCSA). A 55-nm 1-Mb ReRAM-CIM macro was fabricated to demonstrate the MAC operation of 2-b-input, 3-b-weight with 4-b-out. This nvCIM macro achieved T MAC = 14.6 ns at 4-b-out with peak energy efficiency of 53.17 TOPS/W.