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JSSC 2020第2期Other65nm

A Discrete-Time Audio  Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques Song Ma

一种采用动态放大器速度增强技术的离散时间音频ΔΣ调制器
65nm CMOS, 0.8V, 49μW, 91dB DR, 89.6dB SNDR
ΔΣ调制器动态放大器开关电容积分器闪烁噪声抑制音频应用
改进动态放大器复位方法以消除共模电压下降
引入两个辅助分支提升积分器建立速度
开发两种闪烁噪声抑制技术提升信噪比
Abstract
This article presents a discrete-time second- order  modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm 2 core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49-μW power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.