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JSSC 2020第2期Data Converters40nmPLLVCO

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-

提出一种基于VCO的第二阶连续时间ΔΣ ADC，采用改进DPLL结构，实现高效能转换。
40nm CMOS, 1.1V, 260 MS/s, 69.4 dB SNDR, 5.2-MHz带宽, 0.86 mW
VCOΔΣ ADCDPLLTDC噪声整形
▸采用改进的DPLL结构
▸结合VCO与SRO TDC实现二阶噪声整形
▸引入PFD阵列降低VCO功耗和噪声
Abstract
This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) /Delta1/Sigma1analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by pu