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JSSC 2020第2期Data Converters28nmSAR ADCPipeline ADC

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier Wenning Jiang, Student Member , IEEE,Y a nZ h u , Member , IEEE

一种温度稳定的12位1GS/s SAR辅助流水线ADC,SNDR超过60dB。
28nm CMOS, 1V, 1GS/s, 60dB SNDR, 7.6mW
SAR ADC流水线ADC温度稳定高线性度能效优化
采用三阶段(4b-4b-6b)SAR辅助流水线混合架构提高能效和采样率
高线性开环Gm-R残余放大器结合完全稳定和动态特性,减少温度漂移增益变化
后端级联放大拓扑减小输入寄生电容影响,缩小CDAC尺寸加速转换
Abstract
A temperature-stabilized 12-bit single-channel successive approximation regi ster (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR- assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled an d dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front- end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 ◦Ct o8 0 ◦C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.