An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization Hongying Wang , Student Member , IEEE

Abstract

This article introduces a digitally intensive event- driven quasi-level-crossing (quasi-LC) delta-modulator analog- to-digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks, in which minimiz- ing the average sampling rate for sparse input signals can significantly reduce the power consumed in data transmission, processing, and storage. The proposed AR quasi-LC delta mod- ulator quantizes the residue voltage signal with a 4-bit asynchro- nous successive-approximation-register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algo- rithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent aver- age sampling rate and achieves AR through a digital multi-level comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in the conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of 3 at the edge of the modulator’s signal bandwidth. The proposed modulator is fabricated in 28-nm CMOS and achieves a peak SNDR of 53 dB over a signal bandwidth of 1.42 MHz while consuming 205 µW and an active area of 0.0126 mm 2.