Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS Fahim ur Rahman , Student Member , IEEE

Abstract

This article describes an architecture that auto- nomously sets the operating supply voltage ( Vdd )o fad i g i t a l system for minimum total energy dissipation, inclusive of reg- ulator loss. The technique directly computes the energy per cycle (EPC) delivered by the supply to the system, to guide V dd adjustment for minimum energy-per-cycle point (MEP; voltage: VMEP and frequency: fMEP ) tracking. The proposed approach avoids significant Vdd margins typically required for system operation near-threshold and at sub-threshold Vdd levels by employing a unified clock and power ( UniCaP) architecture that regulates target performance across process, voltage, and tem- perature (PVT) variation with minimal guardband requirements. Measurement results from a 65-nm CMOS test chip demonstrate the V MEP tracking with less than 5 mV of error within the operating voltage range of 0.38–0.58 V . Measurement results also demonstrate the MEP tracking with temperature variation from −30 ◦C to 105 ◦C across varied loading conditions over 20 different test chips.