← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2020第2期Power Management130nm

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Se

通过数字低压差稳压器增强加密引擎的功耗和电磁侧信道分析抗性。
130nm CMOS, 25× TVLA泄漏降低, 3579×/2182×/500× MTD提升
侧信道分析AESSIMON数字低压差稳压器电磁抗性
采用安全感知的数字低压差稳压器(DLDO)增强抗侧信道分析能力
引入随机开关噪声注入器(SNI)和随机参考电压生成器(R-VREF)
结合全数字时钟调制(ADCM)进一步降低泄漏
Abstract
This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resis- tance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit) datapaths and a 128-bit SIMON engine with the bit-serial (1-bit) datapath by an on-die security-aware all-digital low-dropout (DLDO) regulator. The proposed DLDO improves SCA resistance using control-loop-induced perturbations in a nominal DLDO, en