← 返回 JSSC 论文列表JSSC 2020第3期RF & Wireless7nm FinFETPLLPAM-4
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Ap
一款14GHz Bang-Bang数字PLL，集成抖动低于150fs，用于高速有线通信。
14GHz, 143-fs rms抖动, 56-Gb/s PAM-4, 40mW功耗
Bang-Bang数字PLLLC DCO前瞻数字环路滤波器7nm FinFET低抖动
▸采用LC型数字控制振荡器（DCO），实现低相位噪声和高频率分辨率
▸前瞻数字环路滤波器大幅降低环路延迟，无需时间数字转换器（TDC）
▸利用7nm FinFET工艺，优化噪声抑制和Q值增强技术
Abstract
Demands for increased wireline data throughput
necessitate multi-gigahertz clock sources of ever-greater fidelity.
This article demonstrates a 14-GHz bang-bang digital phase-
locked loop (BBPLL) with 143-fs rms jitter (integrated from
1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low
jitter is achieved with an LC-based digitally controlled oscillator
(DCO) having a tuning range of 2 GHz, a frequency resolution
of 1.2 MHz/LSB, and a low phase noise of −104 dBc/Hz at 1-MHz
offset. All