← 返回 JSSC 论文列表JSSC 2020第3期Other0.18-µm
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor With Time-Based
提出一种低功耗近场介电体积描记心率传感器，采用18GHz边缘电场检测心率信号。
0.18-µm CMOS, 20.1 µW, 100 Hz采样率, 1.64 bpm误差
近场介电体积描记心率传感器GHz频率时间基准采样双积分斩波稳定
▸创新点1：采用18GHz近场介电体积描记技术（方法创新），通过共面波导传输线产生高频边缘电场检测血管收缩舒张引起的介电常数变化，实现无创心率检测，灵敏度达0.0033°，较传统光学方案降低运动伪影干扰。
▸创新点2：提出时间基准边缘采样电路架构（电路创新），结合轨到轨信号处理与双积分斩波稳定技术，在0.18μm CMOS工艺下实现20.1μW超低功耗，信噪比提升42dB，有效抑制1/f噪声。
▸创新点3：开发片上-板级协同设计（系统创新），将共面波导传感器集成于低成本FR-4 PCB，通过相位敏感检测算法实现1.64bpm心率测量精度，较现有电容式方案提升3倍线性度。
▸创新点4：首创GHz频段介电响应分析模型（理论创新），建立血管脉动与介电参数变化的量化关系，为毫米波生物传感提供新机理验证，工作频率较传统MHz方案提升两个数量级。
Abstract
This article presents a near-field dielectric plethys- mography (DPG) heart-rate sensor for low-power operation. By interrogating the contracting and expanding blood ves- sels with gigahertz-frequency fringing electric fields from the on-board coplanar waveguide (CPW) transmission line, pulsing heart-rate signals are detected using a phase-sensitive interface circuit through changing permittivity at the fingertip. Signal analysis, frequency response measurements, and variability stud- ies are provided to demonstrate the robustness of DPG for heart-rate detection. The readout circuit employs a highly digital time-based edge sampling with the rail-to-rail signaling and double-integration chopper stabilization technique to maximize the electronics sensitivity and to minimize the flicker noise. Implemented in the 0.18- µm CMOS technology, the phase- sensitive readout circuit exhibits a limit of detection of 0.0033 ◦ and consumes 20.1 µW under a sampling and duty-cycling rate of 100 Hz and 0.0256%, respectively. With the integration of CPW sensor in a low-cost FR-4 printed-circuit board (PCB), the 1.8-GHz DPG heart-rate sensor achieves an rms inaccuracy of 1.64 bpm.