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A Bi-Directional- Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS Sy
提出一种双向零延迟自适应时钟电路，用于28nm宽范围AVFS系统，显著降低功耗并减少吞吐量损失。
28nm CMOS, 38.6%–69.4% power gains at near threshold
自适应时钟AVFS系统零延迟功耗优化吞吐量损失
▸创新点1：双向自适应时钟电路通过动态拉伸或压缩时钟周期实现零延迟频率微调，解决了传统AVFS系统在错误恢复时50%吞吐量损失的问题，显著提升了系统能效比。
▸创新点2：基于双延迟线的多相位时钟生成与选择技术，通过时间数字转换器(TDC)和动态OR门实现相位平衡，支持宽频率范围内的精确时钟调节，适应不同PVT条件。
▸创新点3：零延迟错误响应机制结合过渡检测器(TD)锁存器，可在单个时钟周期内完成错误检测与时钟调节，实测显示在近阈值电压下实现38.6%-69.4%的功耗优化。
▸创新点4：动态OR门并行错误收集架构将错误信号处理延迟压缩至半周期，与自适应时钟电路协同工作，消除了传统错误恢复中的时序气泡(throughput bubble)。
Abstract
Resilient circuits based on in situ timing monitoring
adaptive voltage–frequency scaling (A VFS) eliminate excess time
margins caused by process, voltage, and temperature (PVT)
variations but suffer from 50% throughput loss during error
recovery when operating at a half frequency. We propose a
bi-directional adaptive clocking circuit to provide fine frequency
tuning with zero latency for A VFS system. It can either stretch
the clock cycle when there are timing errors to ensure correct
function or