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An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication—Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit Yusang Chun , Student Member , IEEE
提出一种无需均衡器的ISI弹性Dicode编码方案，用于低带宽有线通信。
65-nm CMOS, 2.56-2.66 pJ/bit, 13.6-16 Gb/s, BER < 10^-12
Dicode编码ISI弹性低带宽通信误码率CMOS
▸创新点1：方法创新 - 提出了一种基于Dicode编码的ISI弹性数据编码方案，通过消除连续1或-1的特性，使接收端能够在不使用传统均衡器（FFE/DFE/CTLE）的情况下纠正多比特ISI错误，显著简化了接收机设计。
▸创新点2：系统创新 - 结合Dicode编码与高效纠错逻辑，构建了完整的无均衡器通信系统框架，在24.2dB插入损耗信道下实现BER<10^-12，验证了其在低带宽有线信道中的鲁棒性。
▸创新点3：电路创新 - 采用65nm CMOS工艺实现编解码器，在13.6/16Gb/s速率下分别达到2.56/2.66pJ/bit的超低能耗，证明了该方案在能效比上的硬件优势。
▸创新点4：性能突破 - 通过编码约束与纠错协同设计，首次在无均衡器架构下实现16Gb/s高速通信，插入损耗容忍度达21.4dB，为带宽受限信道提供新解决方案。
Abstract
This article presents an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters [feed-forward equalizer (FFE), decision feedback equalization (DFE), and continuous- time linear equalizer (CTLE)]: inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or −1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65-nm CMOS, the proposed digital encoding and decoding approach can achieve bit-error rate (BER) less than 10 −12 while communicating on a channel with an insertion loss of 24.2 and 21.4 dB with 2.56- and 2.66- pJ/bit efficiency while operating at 13.6 and 16 Gb/s, respectively.