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JSSC 2020第4期RF & Wireless10nmTime-Interleaved ADCEqualizer

112-Gb-s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channel

采用10nm FinFET工艺实现的112Gb/s PAM4 ADC基SERDES接收器，支持长距离通信。
112Gb/s, -35dB Nyquist通道, 1e-6预FEC BER
PAM4SERDESADC长距离通信数字均衡
▸创新点1：低噪声谐振模拟前端(AFE)采用28 GHz谐振技术，显著提升高频信号的信噪比，支持长距离传输（-35 dB Nyquist通道），属于电路创新。
▸创新点2：64路时间交织ADC通过高并行采样架构实现112 Gb/s PAM4信号的高精度转换，降低了单个ADC的采样率需求，属于系统架构创新。
▸创新点3：数字均衡技术结合16抽头FFE和1抽头DFE，有效补偿信道损耗，实现1e-6预FEC误码率，属于算法与系统协同创新。
▸创新点4：7 GHz数控振荡器(DCO)的CDR环路设计，提供高精度时钟恢复，确保高速数据同步的稳定性，属于混合信号电路创新。
Abstract
A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digita