JSSC 2020第4期Power Management7nm FinFET CMOSCharge PumpPLL

A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control Chen-Ting Ko , Ting-Kuei Kuan , Ruei-Pin Shen, and Chih-Hsien Chang

7nm FinFET CMOS PLL设计，采用跟踪保持电荷泵和自动环路增益控制，实现388fs抖动和-80dBc参考杂散。

4.0 GHz, 0.9V, 5.9 mW, 388-fs rms抖动, -80 dBc参考杂散

锁相环FinFET抖动参考杂散低功耗

▸创新点1：跟踪保持电荷泵(THCP)（电路创新） - 该设计通过引入新型THCP结构，显著降低了相位噪声至-115-dBc/Hz，同时功耗仅为53 µW，解决了FinFET节点中高栅极电阻和寄生效应的问题。

▸创新点2：自动环路增益控制（系统创新） - 采用自适应环路增益调节技术，动态优化PLL的稳定性和性能，实现了388-fs的极低抖动和-80-dBc的参考杂散抑制。

▸创新点3：低功耗设计（系统创新） - 通过优化电荷泵和环路增益控制，整体PLL功耗仅为5.9 mW（0.9V供电），能效比达到-240.5 dB的优异指标。

▸创新点4：FinFET工艺适配（工艺创新） - 针对7-nm FinFET CMOS工艺的高寄生效应，设计了专门的电路和系统优化方案，实现了高性能与工艺兼容性的平衡。

Abstract

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also impr ove the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only 53 µW, which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fs rms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a ﬁgure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.