A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping

Abstract

This article presents an interstage gain error shaping (GES) technique that can substantially suppress the in-band quantization leakage error caused by the interstage gain error in pipeline analog-to-digital converters (ADCs). It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A prototype ADC equipped with the p