JSSC 2020第4期Power Management22nmLDO

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response Khondker Zakir Ahmed , Harish K. Krishnamurthy

一种基于事件驱动计算控制器的自适应数字LDO稳压器，具有快速瞬态响应。

100 mV droop for 500 mA (2 A/ns di/dt), <20 ns settling times

数字LDO事件驱动瞬态响应自适应控制CMOS

▸创新点1：事件驱动计算控制器（Event-driven Computational Controller, CC）通过实时计算所需功率门（PGs）数量，替代传统的IIR滤波器控制技术，显著提升了瞬态响应速度（<20 ns）和能效，尤其在500 mA负载下仅产生100 mV的电压跌落。

▸创新点2：确定性两事件持续时间稳定机制（Deterministic Two-event Duration Settling）通过精确控制两个事件的时间间隔，确保输出电压在任意负载或参考瞬态下快速稳定（~ns级），且不受负载动态范围或输出电容值的限制。

▸创新点3：工艺-电压-温度（PVT）自适应设计通过动态调整计算控制器的参数，有效补偿工艺偏差、电压波动和温度变化的影响，支持宽动态电压频率调节（DVFS），提升了系统的鲁棒性和适应性。

▸创新点4：10位功率门（PG）量化设计结合高精度数字控制，在22nm CMOS工艺下实现低静态功耗（未明确数值）与高瞬态响应性能（2 A/ns di/dt），为数字LDO的小型化和集成化提供了新思路。

Abstract

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computa- tional controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR ﬁlter- based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ∼ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns di /dt ) with settling times <20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.