Abstract
A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Ze hnder mod- ulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference- less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in Manuscript received August 15, 2019; revised November 6, 2019 and December 8, 2019; accepted January 5, 2020. Date of publication January 29, 2020; date of current version April 23, 2020. This article was approved by Guest Editor Hongtao Xu. This work was supported in part by the Pioneer Hundred Talents Program, Chi nese Academy of Sciences, in part by the National Natural Scienc e Foundation of China under Grant 61874115, in part by the Beijing Municipal Science and Technology Project under Grant Z191100004819006, in part by the Open Foundation of the State Key Laboratory of Optical Communication Technologies and Networks, Wuhan Research Institute of Posts and Telecommunications, under Grant 2017OCTN- 02, and in part by the joint-lab with P hotonIC Technologies, Inc., Shanghai, China. (Corresponding author: Nan Qi.) Qiwen Liao, Nan Qi, Jian Liu, and Nanjian Wu are with the State Key Laboratory