JSSC 2020第6期Power Management40nmCharge PumpPLL

A 065-V 12-16-GHz Sub-Sampling PLL With 564-fsrms Integrated Jitter and -2564-dB

一种0.65V供电、12-16GHz调谐范围的亚采样锁相环，具有564fs抖动和低功耗特性

40nm CMOS, 0.65V, 12-16GHz, 56.4fs抖动, 7.2mW功耗

亚采样锁相环低压设计抖动优化电源稳定性CMOS工艺

▸混合双路径环路架构解决低压电荷泵输出范围限制

▸低压亚采样电荷泵设计降低抖动

▸电源电压变化下抖动稳定性优化

Abstract

This article presents a low-voltage (LV) sub- sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub- sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC-based voltage-controlled oscillator, are proposed to simultaneously reduce th