A 14-bit 4-MS-s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch C

Abstract

This article presents a 14-bit 4-MS/s voltage- controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behav- ioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastability is of unique characteristics as compared to voltage-domain comparators, and the metastability