A 1.87-mm 2 56.9-GOPS Accelerator for Solving Partial Differential Equations Thomas Chen , Student Member , IEEE, Jacob Botimer, Student Member , IEEE, Teyuh Chou , Student Member , IEEE

Abstract

Solving partial differential equations (PDEs) require high-precision numerical iterations that are demanding in both computation and memory. We apply the multigrid method with a hybrid layer update to reduce iterations and improve speed, and to transform both fine and coarse grids to a residual form to reduce the precision requirement. The reduced precision enables the mapping of a high-precision PDE solver on SRAMs that perform low-precision parallel multiply-accumulates (MACs) in memory, reducing both energy and area. We employ a delay-locked loop to generate well-controlled unit pulses for driving word lines and a dual-ramp single-slope analog-to- digital converter (ADC) to convert bitline outputs. The design is prototyped in a 1.87-mm 2 180-nm test chip made of four 320 × 64 MAC SRAMs, each supporting 128 × parallel 5 b × 5 b MACs with 32 5-b output ADCs and consuming 16.6 mW at 200 MHz. The test chip is demonstrated to reach an error tolerance of 10 −8 in solving PDEs at a grid update rate of 1.38-G entries/s.