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A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications
提出一种超低功耗电容MEMS加速度计模拟前端芯片，采用前馈噪声消除技术降低噪声。
290 µg/√Hz噪声基底，252 nW功耗，65 dB动态范围，62.8 µg偏置不稳定性
超低功耗电容MEMS加速度计前馈噪声消除自平衡桥动态范围
▸创新点1：前馈噪声消除技术（FNRT）是一种电路创新，通过主动抵消相关噪声源，显著降低系统噪声基底至290-µg/√Hz，同时不增加额外功耗（252-nW）。该方法通过分析噪声相关性，在传统自平衡桥架构中引入前馈路径实现噪声抵消。
▸创新点2：改进的自平衡桥架构（SBB）属于电路拓扑创新，通过结构优化在保持原有功能的同时降低对放大器噪声性能的要求，从而减少系统总功耗。该设计在0.18-µm CMOS工艺下实现62.8-µg的偏置不稳定性。
▸创新点3：动态配置与占空比操作系统创新，通过有限状态机（FSM）实现工作模式智能切换，在65dB动态范围内优化功耗分配。该技术使系统能根据信号特征自动调整采样率和处理资源。
▸创新点4：SAR ADC采用信噪比增强技术（方法创新），通过改进量化策略在低功耗条件下提升转换精度，支持系统整体噪声性能的达成。
Abstract
An ultra-low-power (ULP) capacitive micro- electromechanical systems (MEMS) accelerometer analog front-end (AFE) chip with 290- µg/√Hz noise floor and 252-nW power consumption is presented. To achieve such low-noise characteristics under ULP operation, the proposed AFE utilizes a novel circuitry scheme, namely, feedforward noise reduction technique (FNRT), which cancels some of the correlated noise. The FNRT is a simple modification of the conventional self-balancing bridge (SBB) architecture without using any extra power and it can relax the noise requirement on amplifiers in AFE, thereby reducing its power consumption. The designed system uses an SAR ADC employing a simple signal-to-noise ratio (SNR) enhancement technique and includes a finite state machine (FSM) to enable dynamic configuration and duty-cycling operation. The AFE chip is implemented in a 0.18- µm complementary metal–oxide–semico nductor (CMOS) process and achieves a dynamic range of 65 dB and the bias instability of 62.8 µg.