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A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 72-pF
提出一种采用PMOS和NMOS阵列的数字低压差稳压器，实现亚飞秒级速度指标。
28nm CMOS, 0.9V输入电压, 140mA负载电流, 88.4mA负载转换时88mV下冲/42mV过冲
数字低压差稳压器PMOS阵列NMOS阵列速度指标电平移位器
▸使用分段PMOS开关增强NMOS阵列
▸基于电压倍增器的周期性刷新电平移位器减少总电容
▸在28nm CMOS工艺下实现0.12-fs速度指标
Abstract
A digital low-dropout (DLDO) regulator using
p-type MOS (PMOS) and n-type MOS (NMOS) switches is
proposed to achieve a sub-fs speed figure-of-merit (FoM) by
reducing the total capacitance ( C
TOT) and accomplishing a com-
parable output voltage droop ( VOUT) during a load transition.
The proposed DLDO uses the segmented PMOS switches to
fully turn on the NMOS array, whic h strengthens the intrinsic
NMOS loop and maintains the undershoot and overshoot voltages
of 88 and 42 mV , respectively, duri