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A 4-GS-s 399-dB SNDR 117-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ri
一种高效的两步混合电压-时间ADC，在28nm CMOS工艺下实现4GS/s转换速度和39.9dB SNDR。
28nm CMOS, 4GS/s, 39.9dB SNDR, 47.8dB SFDR, 117mW
混合ADC电压-时间转换时间-数字转换高速转换低功耗
▸采用流水线时间转换器（TBC）结构
▸基于电流源的电压-时间转换器（VTC）
▸环形振荡器（RO）时间-数字转换器（TDC）
Abstract
A power and area efficient two-step hybrid
voltage–time ADC achieves a 4-GS/s conversion speed and
39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based
converters (TBCs) with a thermometer capacitive DAC (CDAC)
in the ADC lead to a high-speed and low-power operation. The
pipelined architecture splits the full ADC resolution, thus relaxing
the TBC complexity. The TBC consists of a voltage-domain com-
parator, a current-source-based voltage-to-time converter (VTC),
and a ring oscillator (RO)-based