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A 50-112-Gb-s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
65nm CMOS工艺下实现50-112Gb/s PAM-4发射机，采用分数间隔FFE提升眼图性能
112Gb/s最高数据速率，2.17pJ/bit能效
PAM-4发射机分数间隔FFE电流模式眼图优化65nm CMOS
▸采用两抽头分数间隔前馈均衡器(FFE)，扩展补偿范围至奈奎斯特频率以上且不放大噪声
▸基于粗-细电容阵列的延迟单元调节抽头延迟，位于四分之一速率时钟路径
▸使用线性度优化的FFE驱动器克服沟道长度调制引起的电流压缩
Abstract
This article presents a 50–112-Gb/s current-mode
four-level pulse amplitude modulation (PAM-4) transmitter with
a two-tap fractional-spaced feed-forward equalizer (FFE). The
principle analysis shows that the fractional-spaced FFE can
provide an extended compensation range beyond the Nyquist
frequency without amplifying noise. For the transmitter proto-
type implementation, the tap delay is adjusted by a coarse–fine
capacitor array-based delay cell located in the quarter-rate clock
path. Dynamic l