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JSSC 2020第7期Other10nm

An All-Digital, VMAX-Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of V oltage Droop

一种采用分布式电荷注入方案的全数字VMAX兼容稳定可扩展设计,用于快速缓解电压跌落。
0.8 V/1.4 GHz, 1.0 V/2.0 GHz, 跌落减少74% (45%)
电压跌落电荷注入数字跌落检测器分布式控制CMOS
创新点1:分布式电荷注入(CI)方案采用分布式VMAX兼容CI钳位电路,通过从额外高压轨(如1.8V)快速注入电荷至VCC,实现电压跌落的即时缓解,属于电路创新。测试芯片在0.8V/1.4GHz下实现高达74%的跌落减少。
创新点2:分布式数字跌落检测器(DDD)通过本地化检测附近电压跌落并快速触发关联CI钳位,显著缩短响应时间,属于方法创新。该设计在热点过渡场景下仍能实现38%的跌落减少。
创新点3:分布式跌落控制器系统通过协调多个控制器,在CI触发后逐步让电压调节器接管工作,确保系统稳定运行,属于系统架构创新。理论分析和仿真验证了分布式CI操作的稳定性条件。
创新点4:整体方案通过协同优化CI、DDD和控制器,在10nm工艺测试芯片中实现11%的功耗节省(相比保护带基线),展现显著的能效提升,属于系统级能效创新。
Abstract
Distributed charge injection (CI) scheme featuring distributed VMAX -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to V CC for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of ∼11% over a guard-banded baseline.