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JSSC 2020第7期RF & Wireless65nmHigh-Speed LinkEqualizer

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for C

提出一种基于时钟域编码的iPWM线编码方案，实现低电压下的高效均衡。
3–16 Gb/s, 0.5-0.9V, 27dB channel loss, 1.8 pJ/bit
iPWM线编码时钟域编码低电压均衡
▸创新点1：时钟域iPWM线编码方案（方法创新）。该方案通过将集成脉宽调制（iPWM）应用于时钟域，实现了低电压下的均衡操作，显著降低了功耗。
▸创新点2：将均衡逻辑从数据路径移至子速率时钟路径（系统创新）。这一设计避免了传统均衡器在高带宽数据路径上的性能瓶颈，提升了系统的整体效率。
▸创新点3：低电压操作能力（电路创新）。该收发器在0.5至0.9V的低电压范围内工作，支持3-16 Gb/s的数据速率，展示了其在低功耗应用中的潜力。
▸创新点4：高效能实现（性能创新）。在0.65V电压下，该收发器能以10 Gb/s的速率均衡高达27 dB的信道损耗，能效为1.8 pJ/bit，显著优于传统方案。
Abstract
This article presents a clock-domain-based inte- grated pulsewidth modulation (PWM) (iPWM) line-coding scheme to enable equalization while operating at low supply volt- ages. While conventional equalizers such as feedforward equal- izer (FFE), decision feedback equalizer (DFE), and continuous- time linear equalizer (CTLE) are present on the high-bandwidth data path, the proposed iPWM-based line-coding-based approach moved the equalization logic away from the data path and into the subrate clock