Low-Power Highly Selective Channel Filtering Using a Transconductor–Capacitor Analog FIR

Abstract

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single—time-varying— transconductance and integration capacitor. The transconduc- tance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete trans- fer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, h a sa na c t i v ea r e ao f0 . 0 9m m 2. Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 µWf r o m a 700-mV s upply. This low power consumption is combined with a high selectivity: f −60 dB/f−3d B = 3.8. The filter has 31.5-dB gain and 12-nV/ √ Hz input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an −3.7-dBm out-of-band input signal while still providing >60 dB of filtering.