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A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced V ariation of Decision Threshold V oltage Jung Min Y oon , Student Member , IEEE, Hyungrok Do, Student Member , IEEE, Daehyun Koh, Student Member , IEEE, Seung Han Oak
一种采用耦合电容抵消偏移的DRAM感应放大器,减少阈值电压随机变化的影响。
65nm CMOS
DRAM感应放大器耦合电容偏移抵消阈值电压变化
▸使用耦合电容存储并抵消放大晶体管阈值电压随机变化引起的偏移
▸通过分析决策阈值电压的平均值和标准差优化DRAM感应方案
▸耦合电容同时补偿感应放大器随机偏移和位线电容不匹配的影响
Abstract
This article reports an offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors. Analytical calculations of the average and standard deviation of the decision threshold voltages, defined as the voltage in the cell capacitor that bifurcates into binary levels when activated, are performed on various DRAM sensing schemes and their comparison results are presented. Based on the analysis, the proposed sense amplifier scheme using coupling capacitors is shown to offer the least amount of variation in the decision threshold, thereby increasing the sensing margin of the overall DRAM design. The coupling capacitors not only compensate for the random offset of the sense amplifiers but also mitigate the effect of the mismatch of the bitline capacitances in the open bitline scheme. Measurement on the experimental chip fabricated in a 65-nm CMOS process validates the analysis and confirms the superior performance of the proposed DRAM sensing scheme.