JSSC 2020第8期Data Converters28nmSAR ADC

A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive

一种采用旁路窗口和自适应校准的高效时间交织SAR ADC

28nm FDSOI, 0.9V, 2.4GS/s, 10-bit, 49.02dB SNDR, 9.8mW

时间交织SAR ADC自适应校准非二进制DAC功耗优化

▸定制非二进制DAC引入预定义旁路窗口以降低功耗

▸采用双比较器结构和自适应校准提升速度

▸预充电参考电压池避免通道间串扰

Abstract

This article reports a power-efﬁcient 8 × time- interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efﬁciency and conversion rate, several enhancement techniques are presented. First, a pre-deﬁned bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window