A V ariation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS Cheng-Y ao Hong and Tsung-Te Liu

Abstract

This article presents a variation-resilient micro- processor architecture with a two-level timing error detection and correction (EDAC) system. The proposed EDAC system first performs circuit-level error correction through time bor- rowing when a timing error occurs and subsequently employs a system-level error correction scheme if the timing error is relatively large and cannot be resolved within a cycle. Therefore, compared with the existing EDAC approaches, a processor using the proposed EDAC system can achieve better performance and energy efficiency under different operating conditions without incurring significant implementation effort and overhead. The proposed EDAC system was designed and implemented on an ARM Cortex-M0 microprocessor using a 28-nm CMOS process. The measurement results show that the proposed processor achieves 60.5% reduction in energy by operating under a 0.36-V lower supply voltage and at the same frequency as the baseline processor. In addition, it achieves a 37.1% reduction in minimum energy consumption compared to the baseline design.