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Catena A Near-Threshold Sub-04-mW 16-Core Programmable Spatial Array Accelerator
Catena是一款近阈值电压16核可编程空间阵列加速器，专为超低功耗移动和嵌入式物联网应用设计。
65nm低功耗CMOS, 228 pJ/cycle, 2.7倍能效提升
近阈值电压可编程空间阵列超低功耗物联网能效优化
▸创新点1：采用近阈值电压设计，显著降低功耗，适用于超低功耗移动和嵌入式物联网应用，具体实现为在65nm低功耗CMOS工艺下达到228pJ/cycle的能效。
▸创新点2：优化电路和架构以减少能量浪费，通过减少未充分利用和常开硬件的能量消耗，提升整体能效，相比同类架构能效提升2.7倍。
▸创新点3：提升大规模并行空间架构的能效，通过电路和架构技术的结合，有效解决了大规模并行架构在超低电压操作下的能量浪费问题。
▸创新点4：设计并原型化Catena，验证了所提技术的有效性，展示了其在超低功耗应用中的实际性能表现。
Abstract
In this article, we present Catena, a near-threshold
voltage 16-core programmable spatial array accelerator support-
ing workloads for ultralow-power (ULP) mobile and embedded
Internet of Things applications. We observe that employing
supply voltage scaling alone in a large-scale, massively parallel
spatial architecture, such as Catena, results in marginal runtime
energy efficiency. The reason is that ultralow-voltage operation
magnifies the energy waste of underutilized and always-on hard-
ware i