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JSSC 2020第8期RF & Wireless65nmPhased ArrayNeural Network Accelerator

Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers Susnata Mondal , Student Member , IEEE

毫米波MIMO收发器的功率效率优化与全双工设计技术
28-/37-/39-GHz, 65nm CMOS, 16-/11-dB RX增益, 6.2-/7-dB NF
毫米波MIMO全双工功率效率自干扰消除
首次发现DBF和FC-HBF发射机的PAPR高于PC-HBF
提出内置双频段自干扰消除机制
低损耗宽带天线接口设计和双频段功率合成PA
Abstract
This article describes system and circuit design techniques to enhance power efficiency and incorporate new features in millimeter-wave multi-input–multi-output (MIMO) transceivers. The higher peak-to-average power ratio (PAPR) of the signal transmitted from a digital beamformer (DBF) or a fully connected hybrid beamforming (FC-HBF) transmitter compared with the conventional partially connected hybrid beamforming (PC-HBF) transmitter is identified for the first time. It is then shown that when a power amplifier (PA) with better back-off efficiency than Class-A PA is used, the overall power efficiency of the FC-HBF is superior to the PC-HBF for a given antenna geometry. Second, a new mechanism for built-in dual-band, per-element self-interference cancellation (SIC) is introduced to enable multi-antenna frequency-division-duplex (FDD) and full- duplex (FD) operation. Such SIC can only be supported in the proposed FC-HBF architecture. Several innovative circuit concepts are introduced, including low-loss wideband antenna interface design, dual-band power combining PA, dual-band RF-SIC design, and bidirectional MIMO signal path design. To demonstrate these techniques, a 28-/37-/39-GHz bidirectional two-stream front-end single-element prototype is designed in the 65-nm CMOS. The prototype can be configured as a transmit (TX) or receive (RX) element in DBFs or FC-HBFs which can in turn be configured to support TDD, FDD, or FD operation. The front-end achieves 16-/11-dB RX gain, 6.2-/7-dB N