JSSC 2020第9期Digital Circuits65nmNeural Network Accelerator

A 0.032-mm2 43.3-fJ/Step 100–200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters

基于被动N路径滤波器的带通ΔΣ调制器，实现高能效和宽频调谐范围。

65nm CMOS, 0.032mm², 100-200MHz IF, 2MHz带宽, 55.5dB SNDR, 150µW

带通ΔΣ调制器被动N路径滤波器高能效宽频调谐小面积

▸创新点1：采用被动N路径滤波器实现谐振器，显著提升功率效率并减小面积（0.032 mm²），同时支持100-200 MHz宽中频调谐范围（方法创新）

▸创新点2：仅需单一开环放大器作为有源元件，通过全局负反馈和前置被动N路径滤波器降低输入幅度，减少功耗至150 µW并放宽开关设计约束（电路创新）

▸创新点3：建立线性周期时变系统模型，量化分析非理想特性，为被动N路径DSM设计提供理论框架（理论创新）

▸创新点4：在65nm CMOS工艺下实现433-fJ/step能效，SNDR达60.5 dB（175MHz时），Walden FoM为43.3 fJ/conv-step（性能创新）

Abstract

In this article, we demonstrate a bandpass (BP) delta–sigma modulator (DSM) using passive N-path ﬁlters to implement resonators for high power efﬁciency, wide intermediate-frequency (IF) tuning range, and small area. The fourth-order modulator loop requires only one active element: an open-loop ampliﬁer. The input magnitude of the ampliﬁer is small due to the modulator’s global negative feedback and the passive N-path ﬁlter preceding it. This lowers the power consumption of the ampliﬁer and relaxes the design constraints of the switches in the N-path ﬁlter. A system model of the linear periodically time-variant structure of the proposed modulator is developed, and its nonidealities are analyzed. A BP DSM prototype realized in a 65-nm CMOS with an active area of 0.032 mm 2 features an IF tunable from 100 to 200 MHz with a sampling frequency ranging from 400 to 800 MHz. Over a ﬁxed 2-MHz bandwidth, the modulator achieves a signal to noise and distortion ratio (SNDR) greater than 55.5 dB over the entire IF range. A maximal SNDR of 60.5 dB is achieved at 175-MHz IF while consuming 150 µW, which corresponds to a Walden’s and Schreier’s ﬁgure of merits of 43.3 fJ/conv-step and 164.4 dB, respectively.