A Programmable Heteroge neous Microprocessor Based on Bit-Scalable In-Memory Computing Hongyang Jia , Student Member , IEEE, Hossein Valavi , Student Member , IEEE, Yinqi Tang , Student Member , IEEE, Jintao Zhang , Student Member , IEEE,a n dN a v e e nV e r m a ,Member , IEEE

Abstract

In-memory computing (IMC) addresses the cost of accessing data from memory in a manner that introduces a tradeoff between energy/throughput and computation signal-to- noise ratio (SNR). However, low SNR posed a primary restric- tion to integrating IMC in larger, heterogeneous architectures required for practical workloads due to the challenges with creating robust abstractions necessary for the hardware and software stack. This work exploits recent progress in high-SNR IMC to achieve a programmable heterogeneous microprocessor architecture implemented in 65-nm CMOS and corresponding interfaces to the software that enables mapping of application workloads. The architecture consists of a 590-Kb IMC accelera- tor, configurable digital near-memory-computing (NMC) acceler- ator, RISC-V CPU, and other peripherals. To enable programma- bility, microarchitectural design of the IMC accelerator provides the integration in the standard processor memory space, area- and energy-efficient analog-to-digital conversion for interfacing to NMC, bit-scalable computation (1–8 b), and input-vector sparsity-proportional energy consumption. The IMC accelerator demonstrates excellent matching between computed outputs and idealized software-modeled outputs, at 1b TOPS/W of 192 |400 and 1b-TOPS/mm 2 of 0.60| 0.24 for MAC hardware, at VDD of 1.2|0.85 V , both of which scale directly with the bit precision of the input vector and matrix elements. Software libraries devel- oped for application mapping are