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An 11-b 100-MSs Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Ampli
一种采用高线性度动态放大器的11位100MS/s全动态流水线ADC
28nm CMOS, 0.05mm², 100MS/s, 62dB SNDR, 77dB SFDR, 1.33mW
动态放大器流水线ADC数字增益校正高线性度能效优化
▸创新点1:高线性度动态放大器(电路创新)。采用宽输入范围和动态操作技术,显著提升放大器的线性度,支持ADC的高效能流水线处理,无需增益线性校准,实现62dB的信噪失真比和77dB的无杂散动态范围。
▸创新点2:数字增益校正技术(系统创新)。通过模拟域电压增益控制和数字增益校正码,简化了对工艺、电压和温度变化的补偿,提升了系统的稳定性和适应性,功耗仅为1.33mW。
▸创新点3:无专用硬件的稳定共模输出(方法创新)。提出的开关技术在不增加专用硬件的情况下,实现了稳定的共模输出,降低了电路复杂度和面积,芯片面积仅为0.05mm²。
▸创新点4:全动态流水线ADC设计(系统创新)。采用开环动态放大器,实现了11位100MS/s的全动态流水线ADC,Walden品质因数为10.8-13.1fJ/转换步,展现了高效的能源利用率。
Abstract
This article reports a high-linearity dynamic ampli-
fier with a gain control technique for pipelined analog-to-digital
converters (ADCs). The wide input range and dynamic operation
of the amplifier allow the ADC energy-efficient pipeline process.
The voltage gain is controlled in the analog domain with digital
gain correction codes, enabling simple compensation for process,
voltage, and temperature variations. The proposed switching
technique for the amplifier also defines a stable common-mode
outpu