← 返回 JSSC 论文列表JSSC 2020第9期Data Converters180nmDelta-Sigma ADCDAC
Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters Wit
提出高分辨率连续时间ΔΣ转换器设计技术，解决寄生电阻、符号间干扰和闪烁噪声问题。
180nm CMOS, 32MS/s, 24mW, 108dB SNR
连续时间ΔΣ转换器高分辨率寄生电阻符号间干扰闪烁噪声
▸创新点1：虚拟地切换电阻DAC，通过减少参考路径中的寄生电阻和降低反馈DAC波形中的符号间干扰（ISI），显著降低了失真，属于电路创新。
▸创新点2：输入OTA的斩波技术，通过斩波第一级输入OTA，有效降低了闪烁噪声，提升了信噪比，属于电路创新。
▸创新点3：三阶段OTA和FIR反馈，采用三阶段OTA和有限脉冲响应（FIR）反馈，减少了斩波伪影和时钟抖动敏感性，属于系统创新。
▸创新点4：设计的高分辨率连续时间Delta-Sigma转换器在180 nm CMOS工艺下实现了250 kHz带宽和108 dB SNDR，性能指标优异，属于系统创新。
Abstract
We present design considerations for CTMs that
attempt to achieve high resolution (16 + bits) over a wide
bandwidth (>200 kHz), resulting in a low in-band noise spectral
density. The main challenges in such designs are parasitic
resistance in the reference path, inter-symbol interference (ISI)
in the feedback-digital-to-analog converter (DAC) waveform, and
flicker noise of the input operational transconductance amplifier
(OTA). We introduce the virtual-ground-switched resistor DAC
as a way to ac