Abstract
CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number of neurons in parallel but only extracellularly with a low signal-to-noise ratio. Patch-clamp electrodes can perform intracellular recording with a high signal-to-noise ratio but only from a few neurons in parallel. Recently, we have developed and reported a neuro- electronic interface that combines the parallelism of the CMOS MEA and the intracellular sensitivity of the patch clamp. Here, we report the design and characterization of the CMOS inte- grated circuit (IC), a critical component of the neuroelectronic interface. Fabricated in 0.18- µm technology, the IC features an array of 4096 platinum black (PtB) nanoelectrodes spaced at a 20- µm pitch on its surface and contains 4096 active pixel circuits. Each active pixel circuit, consisting of a new switched- capacitor current injector—-capable of injecting from ±15 pA to ±0.7 µA with a 5-pA resolution—-and an operational amplifier, Manuscript received August 27, 2019; revised November 27, 2019 and March 30, 2020; accepted May 10, 2020. This article was approved by Associate Editor David Stoppa. This work was supported in part by the Samsung Advanced Institute of Technology, Samsung Electronics, under Grant A37734 and Grant A37738, in part by the Army Research Office under Grant W911NF-15-1-0565 and Grant W911NF-15-1-0548, in part by the National Science Foundation under Grant DGE1745303, in part by the National Institutes of Health