A 20-GHz 1.9-mW LNA Using gm-Boost and Current-Reuse Techniques in 65-nm CMOS for

Abstract

A 20-GHz low-power low-noise amplifier (LNA) in 65-nm CMOS is presented. The LNA is cascaded with a single-ended gm-boosted common-gate (CG) stage and a differential neutralized common-source (CS) stage. Current- reuse technique is employed to save the power consumption with little deterioration in gain and noise figure (NF). The transformer-based g m-boost technique in the CG stage and neutralization technique in CS stage further enhances the RF performances. Inter-stage magnetically coupled resonator (MCR) extends the bandwidth. An elaborate analysis of the current-reused CG–CS LNA using a transformer-based g m-boost technique and transformer-based MCR is proposed. Fabricated in 65-nm CMOS technology, the LNA achieves a measured power gain of 14.9 dB at 21 GHz with a −3-dB bandwidth of 4.8 GHz. The lowest NF is 3.3 dB at 19.5 GHz and is below 4d Bf r o m1 7t o2 1G H z .T h eL N Ac o n s u m e s1 . 9m Wf r o ma 1-V supply, with a chip area of 600 μm × 700 μm.