JSSC 2020第10期Clocking & PLLs40nmPLLCDR

A 32-Gbs 046-pJbit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Sel

本文提出了一种四电平脉冲幅度调制(PAM4)四分之一速率时钟和数据恢复电路(CDR)，采用线性相位检测器和自偏置PLL多相时钟发生器，实现了低功耗和低抖动。

40nm CMOS, 32-Gb/s, 0.46 pJ/bit, 352.6 fs抖动

PAM4时钟和数据恢复线性相位检测器自偏置PLL低抖动

▸四分之一速率线性相位检测器(QLPD)消除抖动

▸自偏置PLL多相时钟发生器(MCG)降低功耗

▸宽环路带宽(约600 MHz)生成低抖动多相时钟

Abstract

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jit- ter of the bang-bang PD. A self-biased phase-locked loop (PLL)- based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quar